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NXP Semiconductors /LPC5410x /MAILBOX /IRQ1

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Interpret as IRQ1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTREQ

Description

Interrupt request register for the Cortex M4 CPU.

Fields

INTREQ

If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data